Gate Level Power Estimation

The Gate Level power estimation is carried out by the Synopsys Power Compiler, which is included in the framework of the Synopsys Design Compiler. This figure shows the basic flow should be followed.

These guidelines are for verilog / vhdl sources. You also need:

"Synopsys Design Compiler (DC)"
"Cadence NCVerilog"

If you're a student at University of Victoria, you can find some instructions about these tools at the bottom of the page.

If you have your tools set up and ready to use, keep going...

To obtain gate level power estimation, you need to first synthesize your code. Then simulate the code, obtaining all the switching activities, then by using design compiler, estimate the energy consumption of your design.

Let's assume you want to estimate energy consumption of your design, called MyDesign. Also, it is written in verilog. Now, all you need to do is:

Synthesize & Forward SAIF Generation:
You can synthesize your code using DC's GUI, or the better way, using the command prompt.
Run DC's shell:
> dc_shell-t
Then you need to run fw.scr script file to compile your code (change the script content according to your design):
dc_shell> source fw.scr
Using this script, you generate three essential files:
1. Synthesized verilog file ( MyDesign_syn.v ): which contains all your design and all the modules used from any library.
2. Your design ".db" file: This file is used later at the power report step.
3. Your forward ".saif" file: Just know this file is used in simulation.
Simulation & Backward SAIF Generation:
You need your synthesized design and forward SAIF files for simulation. Also, you need to make a test bench for your design, to actually simulate it!
You need to make your test bench file in verilog format, using MyDesign_tb.v template. One important thing to consider is to load your libraries' SAIF files in your test bench.
Usually, you don't have these SAIF files, and need to make then, using the following command in DC's command prompt:
dc_shell> lib2saif -output YOUR_LIBRARY.saif YOUR_LIBRARY.db
Then you need to load these generated SAIF files into your test file, using the "$read_lib_saif" command at line 17 in the test bench template.
Now, all you need to do is to run your simulation, which is done by ncverilog. You need to get into Cadence's command prompt and run:
> ncverilog +ncacces+r +loadpli1=$SYNOPSYS/auxx/syn/power/vpower/lib-$ARCH/libvpower.so:saifpli_bootstrap {LIBRARY_VERILOG_FILES} MyDesign_syn.v +ncaccess+r MyDesign_tb.v
Note that $SYNOPSYS variable should be set to your SYNOPSYS directory. Also, $ARCH is your system architecture, like "linux", "sparcOS5", "suse32", etc.

When the simulation is done, the command at line 40 of the template test bench file has generated your backward SAIF file. This file contains all the switching activities during simulation.
Power Report:
Now that you have your backward SAIF file and your ".db" file, you can have the power report. You need to run bw.scr script file:
dc_shell> source bw.scr
That's it. Now you see the power report on the DC's shell.

Troubleshooting

If you see errors, related to the scripts, it might be because of your DC's operation mode. You need to exchange these commands:

From	To
source	include
set power_preserve_rtl_hier_names true	power_preserve_rtl_hier_names = true
read_db	read -format db

UVic Tools Setup

You have to keep in mind that these instructions are for the facilities at University of Victoria. They might still partly apply to your environment, but not necessarily.

SSH tools
Regardless of the machine you're using, you need to connect remotely to one of these machines:
"cmca.uvic.ca", "cmcb.uvic.ca", "cmcc.uvic.ca" or "cmcd.uvic.ca"
To do so, you need an SSH client. Also, because of graphical interface that Synopsys and Cadence have, you need an XWindow client. An easy to use one is:
Starnet XWin32.
Please download version 7.1, to have the option of "PseudoColor mode" which you need for Cadence environment. You need to go to XWin config menu, under the "Color" tab, check the "PseudoColor Mode" option.
Synopsys / Cadence framework
First, you need to connect using your SSH client to a cmc machine and change to your working directory.
You need to have a synopsys setup file in your working directory, called ".synopsys_dc.setup" . You can download a template that you usually don't need to change from here. Note that this file becomes hidden because of the starting "." in its name.
To run Synopsys environment, you need to run:
shell> /project/cmc/bin/setSYNOPSYS2005.09
To run Cadence environment, you need to run:
shell> /project/cmc/bin/setCADENCE2005a
Note that the version might have changed, so take a list of the "bin" directory and find the appropriate script:
shell> ls /project/cmc/bin
After running the scripts, you see an XWindow popping up, running a shell command prompt.

The architecture ($ARCH) for cmc machines is "sparcOS5" and the Synopsys path ($SYNOPSYS) is "/CMC/tools/synopsys/syn/"